Back-biased face target sputtering based memory data sensing technique

ABSTRACT

Systems and methods are disclosed to form an exemplary memory structure by flowing argon gas and oxygen gas in a deposition chamber; providing a low oxygen flow rate approximately between 0 and ten percent (10%) of an argon flow rate, a pressure approximately between 2×10 −5  Torr and 1×10 −3  Torr, and a deposition temperature approximately between 340° C. and 450° C.; and the composition of sputtering target is PCMO (Pr 1-x Ca x MnO 3 , where X is between 0.1 and 0.9). The process forms a PCMO (Pr 1-x Ca x MnO 3 , X=0.1-0.9) material film on the wafer and a plurality of current sensors coupled to PCMO memory cells.

BACKGROUND

This application is a continuation in part (CIP) application of Ser. No.10/662,862, the content of which is incorporated by reference.

The present invention relates to systems and methods for fabricatingsemiconductor devices at low temperature.

Electronic systems have become a ubiquitous fixture in modern society.These electronic systems range from simple, hand-held calculators tomore complex systems including computers, personal digital assistants(PDAs), embedded controllers and complex satellite imaging andcommunications systems. As noted in U.S. Pat. No. 6,862,211, manyelectronic systems include a microprocessor that performs one or morefunctions based on data provided to the microprocessor. This data istypically stored in a memory device of the electronic system such as acommon dynamic random access memory (DRAM) device. A DRAM typicallyincludes an array of memory cells that store data as binary values,e.g., 1's and 0's. In a conventional DRAM, the data is stored bycontrolling the charge on capacitors in each cell of the DRAM. Data inthe array is “randomly accessible” since a processor can retrieve datafrom any location in memory by providing the appropriate address to thememory device. One problem with conventional DRAM is that the device is“volatile.” This means that when power is turned off to the system usingthe DRAM, the data in the memory device is lost.

In a parallel trend, various semiconductor fabrication steps need to bedone at low temperature. For instance, when applying a ferroelectricthin film to a highly integrated device, conventional processes do notprovide a ferroelectric thin film which sufficiently fulfills variousconditions, such as denseness and evenness on the thin film surfacerequired for fine processing and formation of film at a relatively lowtemperature.

U.S. Pat. No. 5,000,834 discloses a vacuum deposition technique known asface target sputtering to form thin films on magnetic recording heads atlow temperature. The sputtering method is widely used for forming a thinfilm on a substrate made of PMMA because of intimacy between thesubstrate and the thin film formed therethrough. The amorphous thin filmof rare earth—transition metal alloy formed through the sputteringmethod is applied to an erasable magneto-optical recording medium. Thesputtering method is performed as follows: Positive ions of an inert gassuch as Argon (Ar) first created by a glow discharge are acceleratedtoward a cathode or target, and then they impinge upon the target. As aresult of ionic bombardment, neutral atoms and ions are removed from thetarget surface into a vacuum chamber due to the exchange of momentumtherebetween. The liberated or sputtered atoms and ions are consequentlydeposited on a preselected substrate disposed in the vacuum chamber.

U.S. Pat. No. 6,156,172 discloses a plasma generating unit and a compactconfiguration of the combination of plasma space and substrate holdersfor a facing target type sputtering apparatus which includes: anarrangement for defining box-type plasma units supplied therein withsputtering gas mounted on outside wall-plates of a closed vacuum vessel;at least a pair of targets arranged to be spaced apart from and face oneanother within the box-type plasma unit, with each of the targets havinga sputtering surface thereof; a framework for holding five planes of thetargets or a pair of facing targets and three plate-like membersproviding the box-type plasma unit so as to define a predetermined spaceapart from the pair of facing targets and the plate-like members, whichframework is capable of being removably mounted on the outside walls ofthe vacuum vessel with vacuum seals; a holder for the target havingconduits for a coolant; an electric power source for the targets tocause sputtering from the surfaces of the targets; permanent magnetsarranged around each of the pair of targets for generating at least aperpendicular magnetic field extending in a direction perpendicular tothe sputtering surfaces of the facing targets; devices for containingthe permanent magnets with target holders, removably mounted on theframework; and a substrate holder at a position adjacent the outletspace of the sputtering plasma unit in the vacuum vessel. The unifiedconfiguration composed of a cooling device for cooling both the backsideplane of the targets and a container of magnets in connection with theframework improves the compactness of sputtering apparatus.

SUMMARY

In one aspect, systems and methods are disclosed to form an exemplarymemory structure by flowing argon gas and oxygen gas in a depositionchamber; providing a low oxygen flow rate approximately between 0 andten percent (10%) of an argon flow rate, a pressure approximatelybetween 2×10⁻⁵ Torr and 1×10⁻³ Torr, and a deposition temperatureapproximately between 340° C. and 450° C.; and forming a PCMO(Pr_(1-x)Ca_(x)MnO₃, where X is approximately between 0.1 and 0.9)material.

Implementations of the above aspect may include one or more of thefollowing. The PCMO material maintains a uniform ratio of Pr:Ca:Mn:O isacross the PCMO material. A poly-crystalline PCMO can be formed at atemperature below 400° C. with the low oxygen flow rate. A memory devicecan be formed. The PCMO structure includes a layer of with a thicknessof 2,000 Å or less. Materials can be deposited using a radio frequency(RF) rate of 13.56 Megahertz. The method includes providing at least onetarget and a substrate having a film-forming surface portion and a backportion; creating a magnetic field so that the film-forming surfaceportion is placed in the magnetic field with the magnetic field inducednormal to the substrate surface portion; back-biasing the back portionof the substrate; and sputtering material onto the film-forming surfaceportion, wherein the thin forming surface portion comprises non-volatiledata storage devices interconnected thereto.

In another aspect, a facing targets sputtering device for semiconductorfabrication includes an air-tight chamber in which an inert gas isadmittable and exhaustible; a pair of target plates placed at oppositeends of said air-tight chamber respectively so as to face each other andform a plasma region therebetween; a pair of magnets respectivelydisposed adjacent to said target plates such that magnet poles ofdifferent polarities face each other across said plasma region therebyto establish a magnetic field of said plasma region between said targetplates; a substrate holder disposed adjacent to said plasma region, saidsubstrate holder adapted to hold a substrate on which an alloyed thinfilm is to be deposited; and a back-bias power supply coupled to thesubstrate holder.

In another aspect, a method for sputtering a thin film onto a substrateincludes providing at least one target and a substrate having afilm-forming surface portion and a back portion; creating a magneticfield so that the film-forming surface portion is placed in the magneticfield with the magnetic field induced normal to the substrate surfaceportion; back-biasing the back portion of the substrate; and sputteringmaterial onto the film-forming surface portion.

Advantages of the invention may include one or more of the following.The substrate temperature in forming a thin film is approximately below400 degrees C. and the process requires a short time. Since the thinfilm is formed at a very low temperature during substantially the wholeprocess, the process can be applied to a highly integrated device todeposit an additional layer with a plurality of elements withoutdamaging other elements previously deposited using conventionaldeposition.

BRIEF DESCRIPTION OF THE FIGURES

In order that the manner in which the above-recited and other advantagesand features of the invention are obtained, a more particulardescription of the invention briefly described above will be rendered byreference to specific embodiments thereof, which are illustrated, in theappended drawings. Understanding that these drawings depict only typicalembodiments of the invention and are not therefore to be considered tobe limiting of its scope, the invention will be described and explainedwith additional specificity and detail through the use of theaccompanying drawings in which:

FIG. 1 shows one embodiment of an apparatus for fabricatingsemiconductor.

FIG. 2 is an exemplary electron distribution chart.

FIG. 3 shows one embodiment of an FTS unit.

FIG. 4A shows one embodiment of a second apparatus for fabricatingsemiconductor.

FIG. 4B shows one embodiment of a second apparatus for fabricatingsemiconductor.

FIG. 5 shows a TEM image of a cross sectional view of an exemplarydevice fabricated with the system of FIG. 1.

FIG. 6 is an enlarged view of one portion of the TEM image of FIG. 5.

FIG. 7 shows an exemplary memory circuit.

FIG. 8 shows another process for forming a semiconductor device.

FIG. 9 shows an exemplary chart showing the uniformity of the PCMOcomposition formed using the process of FIG. 8.

FIG. 10 shows an exemplary chart showing the effect of the oxygen rateflow and the impact on the PCMO structure.

DESCRIPTION

Referring now to the drawings in greater detail, there is illustratedtherein structure diagrams for a semiconductor processing system andlogic flow diagrams for processes a system will utilize to deposit amemory device at low temperature, as will be more readily understoodfrom a study of the diagrams.

FIG. 1 shows one embodiment of an apparatus for fabricatingsemiconductor. An embodiment reactor 10 is schematically illustrated inFIG. 1. The reactor 10 includes a metal chamber 14 that is electricallygrounded. A wafer or substrate 22 to be sputter coated is supported on apedestal electrode 24 in opposition to the target 16. An electrical biassource 26 is connected to the pedestal electrode 24. Preferably, thebias source 26 is an RF bias source coupled to the pedestal electrode 24through an isolation capacitor. Such bias source produces a negative DCself-bias VB on the pedestal electrode 24 on the order of tens of volts.A working gas such as argon is supplied from a gas source 28 through amass flow controller 30 and thence through a gas inlet 32 into thechamber. A vacuum pump system 34 pumps the chamber through a pumpingport 36.

An FTS unit is positioned to face the wafer 22 and has a plurality ofmagnets 102, 104, 106, and 108. A first target 110 is positioned betweenmagnets 102 and 104, while a second target 120 is positioned betweenmagnets 106 and 108. The first and second targets 110 and 120 define anelectron confining region 130. A power supply 140 is connected to themagnets 102-108 and targets 110-120 so that positive charges areattracted to the targets 110-120. During operation, particles aresputtered onto a substrate 22 which, in one embodiment where the targets110 and 120 are laterally positioned, is vertically positioned relativeto the lateral targets 110 and 120. The substrate 22 is arranged to beperpendicular to the planes of the targets 110 and 120. A substrateholder 24 supports the substrate 22.

The targets 110 and 120 are positioned in the reactor 10 in such amanner that two rectangular shape cathode targets face each other so asto define the plasma confining region 130 therebetween. Magnetic fieldsare then generated to cover vertically the outside of the space betweenfacing target planes by the arrangement of magnets installed in touchwith the backside planes of facing targets 110 and 120. The facingtargets 110 and 120 are used as a cathode, and the shield plates areused as an anode, and the cathode/anode are connected to outputterminals of the direct current (DC) power supply 140. The vacuum vesseland the shield plates are also connected to the anode.

Under pressure, sputtering plasma is formed in the space 130 between thefacing targets 110 and 120 while power from the power source is applied.Since magnetic fields are generated around the peripheral area extendingin a direction perpendicular to the surfaces of facing targets 110 and120, highly energized electrons sputtered from surfaces of the facingtargets 110 and 120 are confined in the space between facing targets 110and 120 to cause increased ionized gases by collision in the space 130.The ionization rate of the sputtering gases corresponds to thedeposition rate of thin films on the substrate 22, then, high ratedeposition is realized due to the confinement of electrons in the space130 between the facing targets. The substrate 22 is arranged so as to beisolated from the plasma space between the facing targets 110 and 120.

Film deposition on the substrate 22 is processed at a low temperaturerange due to a very small number of impingement of plasma from theplasma space and small amount of thermal radiation from the targetplanes. A typical facing target type of sputtering method has superiorproperties of depositing ferromagnetic materials at high rate depositionand low substrate temperature in comparison with a magnetron sputteringmethod. When sufficient target voltage VT is applied, plasma is excitedfrom the argon. The chamber enclosure is grounded. The RF power supply26 to the chuck or pedestal 24 causes an effective DC ‘back-bias’between the wafer and the chamber. This bias is negative, so it repelsthe low-velocity electrons and negative ions, such as O²⁻.

FIG. 2 illustrates an exemplary electron distribution for the apparatusof FIG. 1. The electron distribution follows a standard Maxwelliancurve. Low energy electrons have two characteristics: they are numerousand they tend to have non-elastic collisions with the deposited atoms,resulting in amorphization during deposition. High-energy electrons comethrough the back-biased shield, but they effectively “bounce” off theatoms without significant energy transfer—these electrons do not affectthe way bonds are formed. This is especially true because high energyelectrons spend very little time in the vicinity of the atoms, while thelow energy electrons spend more time next to the atoms and can interferewith bond formation.

The presence of the large positively biased shield affects the plasma,particularly those close to the pedestal electrode 24. As a result, theDC self-bias developed on the pedestal 24, particularly by an RF biassource, may be more positive than for the conventional large groundedshield, that is, less negative since the DC self-bias is negative intypical applications. It is believed that the change in DC self-biasarises from the fact that the positively biased shield drains electronsfrom the plasma, thereby causing the plasma and hence the pedestalelectrode to become more positive.

FIG. 3 shows another embodiment of an FTS system. In this embodiment, awafer 200 is positioned in a chamber 210. The wafer 200 is moved intothe chamber 210 using a robot arm 220. The robot arm 220 places thewafer 200 on a wafer chuck 230. The wafer chuck 230 is moved by a chuckmotor 240. One or more chuck heaters 250 heats the wafer 200 duringprocessing.

Additionally, the wafer 200 is positioned between the heater 250 and amagnetron 260. The magnetron 260 serves as highly efficient sources ofmicrowave energy. In one embodiment, microwave magnetrons employ aconstant magnetic field to produce a rotating electron space charge. Thespace charge interacts with a plurality of microwave resonant cavitiesto generate microwave radiation. One electrical node 270 is provided toa back-bias generator such as the generator 26 of FIG. 1.

In the system of FIG. 3, two target plates are respectively connectedand disposed onto two target holders which are fixed to both inner endsof the chamber 210 so as to make the target plates face each other. Apair of permanent magnets are accommodated in the target holders so asto create a magnetic field therebetween substantially perpendicular tothe surface of the target plates. The wafer 200 is disposed closely tothe magnetic field (which will define a plasma region) so as topreferably face it. The electrons emitted from the both target plates byapplying the voltage are confined between the target plates because ofthe magnetic field to promote the ionization of the inert gas so as toform a plasma region. The positive ions of the inert gas existing in theplasma region are accelerated toward the target plates. The bombardmentof the target plates by the accelerated particles of the inert gas andions thereof causes atoms of the material forming the plates to beemitted. The wafer 200 on which the thin film is to be disposed isplaced around the plasma region, so that the bombardment of these highenergy particles and ions against the thin film plane is avoided becauseof effective confinement of the plasma region by the magnetic field. Theback-bias RF power supply causes an effective DC ‘back-bias’ between thewafer 200 and the chamber 210. This bias is negative, so it repels thelow-velocity electrons.

FIG. 4A shows one embodiment of a second apparatus for fabricatingsemiconductor. In the system of FIG. 4A, multiple 1-D deposition sourcesare stacked in the deposition chamber. The stacking of the sourcesreduces the amount of wafer travel, while significantly increasingdeposition uniformity. A wafer 300 is inserted into a chamber 410 usinga robot arm 420 moving through a transfer chamber 430. The wafer 300 ispositioned onto a rotary chuck 440 with chuck heater(s) 450 positionedabove the wafer. A linear motor 460 moves the chuck through a pluralityof deposition chambers 470.

The system of FIG. 4A provides a plurality of one dimensional sputterdeposition chambers. Each chamber can deposit a line of material. Bymoving the wafer 300 with the linear motor 460, 2-d coverage isobtained.

Turning now to FIG. 4B, a second embodiment of a fabrication apparatusis shown. In this embodiment, a chuck 500 is positioned inside achamber. The chuck 500 supports a wafer 502. The chamber has vacuumbellows 510. The chuck 500 is driven by a wafer rotator 520 whichrotates the wafer 502 and the chuck 500 in a pendulum-like manner. Thechuck 500 is also powered by a linear motor 530 to provide up/downmotion. A plurality of sources 540-544 perform deposition of materialson the wafer 502.

The system of FIG. 4B gets linear motion of the wafer 502 past the threesources for uniform deposition. This is done through a chuck supportedfrom underneath rather than from the side. A jointed pendulum supportsthe wafer and keeps the wafer at a constant vertical distance from thetarget as the pendulum swings. The system swings the wafer using apendulum. The system is more stable than a system with a lateral lineararm since the chuck 500 is heavy and supports the weight of the wafer, aheater, and RF back-bias circuitry and would require a very thicksupport arm otherwise the arm would wobble. Also, the linear arm wouldneed to extend away from the source, resulting in large equipment. Inthis implementation, the arm sits below the chuck, resulting in asmaller piece of equipment and also the arm does not have to supportmuch weight.

In one embodiment, a process for obtain 2D deposition coverage is asfollows:

Receive desired 2D pattern from user

Move chuck into a selected deposition chamber;

Actuate linear motor and rotary chuck to in accordance with the 2Dpattern

Move current wafer to next deposition chamber

Get next wafer into the current chamber and repeat process.

FIG. 5 shows a TEM image of an exemplary device fabricated with thesystem of FIG. 1, while FIG. 6 is an enlarged view of one portion of theTEM image of FIG. 5. The device of FIG. 5 was fabricated at a lowtemperature (below 400° C.). At the bottom of FIG. 5 is an oxide layer(20 nm thick). Above the oxide layer is a metal layer, in this case atitanium layer (24 nm thick). Above this layer is an interface layer, inthis case a platinum (Pt) interface face layer (about 5 nm). Finally, acrystallite PCMO layer (79 nm thick) is formed at the top. Grains inthis layer can be seen extending from the bottom toward the top with aslightly angled tilt. FIG. 6 shows a zoomed view showing the Ti metallayer, the Pt interface layer and the PCMO grain in more details.

Although one back-biased power supply is mentioned, a plurality ofback-bias power supplies can be used. These power supplies can becontrollable independently from each other. The electric energiessupplied can be independently controlled. Therefore, the components ofthe thin film to be formed are easily controlled in every sputteringbatch process. In addition, the composition of the thin film can bechanged in the direction of the thickness of the film by using theFacing Targets Sputtering device.

FIG. 8 shows an exemplary process for forming a memory structure. Theprocess flow argon gas and oxygen gas in a deposition chamber (1400). Alow oxygen flow rate approximately between 0 and ten percent (10%) of anargon flow rate is maintained at a pressure approximately between 2×10⁻⁵Torr and 1×10⁻³ Torr and a deposition temperature approximately between340° C. and 450° C. (1402). The composition of sputtering target is PCMO(Pr_(1-x)Ca_(x)MnO₃, where X is between 0.1 and 0.9). The process formsa PCMO (Pr_(1-x)Ca_(x)MnO₃, X=0.1-0.9) material film on the wafer(1404).

The material has a ratio of Pr:Ca:Mn:O that is highly uniform across thePCMO film. The uniformity is shown in FIG. 9. As shown therein, at adepth of 0.5 microns or less, the ratio is constant. The low oxygen flowallows the system to deposit the poly-crystalline PCMO at a relativelylow temperature below 400° C. The high flow (high partial pressure) ofoxygen (O2) prevent the growth of poly-crystalline under lowtemperature. The reactive sputtering using three target of Pr, Ca and Mnunder high flow of oxygen with Ar can not accomplish the low-temperaturedeposition of crystalline PCMO.

The PCMO deposition method uses a PCMO target under a low oxygen flowthe presence of argon. The oxygen flow is between 0 to 10% of argon. Thelow temperature deposition (T<400° C.) enables memory structures to beformed above semiconductor structures while minimizing potential damageto the preformed semiconductor structures.

FIG. 10 shows an exemplary chart of a plot of PCMO crystalline formationas a percentage of argon and oxygen rate flow parameters at an exemplarytemperature of 340 degrees. As shown therein, when the percentage ofoxygen over argon flow rate is above 20%, the crystalline fraction isaround 20%. At a percentage of 15% or less, the crystalline fractionincreases to between 25% and 95%. The effect of the low flow oxygen oncrystalline formation is shown in the two cross-sectional images of thedeposited structure.

Turning now to the images, the top image of FIG. 10 shows the crystalformation when the flow is all argon. The amorphous or micro-crystallineformation is a relatively small portion of the entire PCMO structure. Incontrast, in the bottom image, when the flow ratio of oxygen to argon isapproximately 15%, the resulting PCMO structure is substantiallyamorphous or micro-crystalline with a small crystal portion. Theamorphous PCMO forms the desired memory structure.

FIG. 11 illustrates a resistance sensing circuit for sensing theresistance value of a resistor-based memory cell, in accordance with afirst exemplary embodiment of the invention. A current source 400delivers a small current (e.g., 1 mA) to the memory array 150 such thateach of the unused row lines 450 of the memory array 150 conductsapproximately 1 uA (i.e., assuming a 1024×1024 array). The row line 500associated with a selected cell 460 is driven to ground. Each of theunused row lines 450 coupled to the column line 230 associated with theselected cell 460 is shorted to the others so that an equivalentresistance of approximately 1 Kohm is read at column line 230.

Turning now to FIG. 12, a flowchart of an operational flow of anexemplary resistance memory containing the memory cell reading circuitof FIG. 10 is depicted. The flow begins at process segment 6000. Atsegment 6100, a cell 460 is selected. One side of the resistor 210 ofthe selected memory cell 460 is grounded by grounding the associatedwordline (row) at segment 6200. At segment 6300, a current is driventhrough all unselected row lines. At segment 6400, a voltage measurementis taken from the column line 230 that is associated with the selectedmemory cell 460 to ground. The measured voltage is compared with areference voltage at segment 6500 to determine the cell resistance valueand, ultimately, the logic value stored in the cell 460. The processflow ends at segment 6600.

It is to be understood that various terms employed in the descriptionherein are interchangeable. Accordingly, the above description of theinvention is illustrative and not limiting. Further modifications willbe apparent to one of ordinary skill in the art in light of thisdisclosure.

The invention has been described in terms of specific examples which areillustrative only and are not to be construed as limiting. The inventionmay be implemented in digital electronic circuitry or in computerhardware, firmware, software, or in combinations of them.

Apparatus of the invention for controlling the fabrication equipment maybe implemented in a computer program product tangibly embodied in amachine-readable storage device for execution by a computer processor;and method steps of the invention may be performed by a computerprocessor executing a program to perform functions of the invention byoperating on input data and generating output. Suitable processorsinclude, by way of example, both general and special purposemicroprocessors. Storage devices suitable for tangibly embodyingcomputer program instructions include all forms of non-volatile memoryincluding, but not limited to: semiconductor memory devices such asEPROM, EEPROM, and flash devices; magnetic disks (fixed, floppy, andremovable); other magnetic media such as tape; optical media such asCD-ROM disks; and magneto-optic devices. Any of the foregoing may besupplemented by, or incorporated in, specially-designedapplication-specific integrated circuits (ASICs) or suitably programmedfield programmable gate arrays (FPGAs).

While the preferred forms of the invention have been shown in thedrawings and described herein, the invention should not be construed aslimited to the specific forms shown and described since variations ofthe preferred forms will be apparent to those skilled in the art. Thusthe scope of the invention is defined by the following claims and theirequivalents.

1. A method for forming a semiconductor, comprising: flowing argon gasand oxygen gas in a deposition chamber; providing a low oxygen flow rateapproximately between 0 and ten percent (10%) of an argon flow rate, apressure approximately between 2×10⁻⁵ Torr and 1×10⁻³ Torr, and adeposition temperature approximately between 340° C. and 450° C.;providing a sputtering target made of PCMO (Pr_(1-x)Ca_(x)MnO₃, where Xis between 0.1 and 0.9); and forming a plurality of current sensorscoupled to an array of PCMO memory cells.
 2. The method of claim 1,wherein the PCMO material maintains a uniform ratio of Pr:Ca:Mn:O isacross the PCMO material.
 3. The method of claim 1, comprising forming apoly-crystalline PCMO at a temperature below 400° C. with the low oxygenflow rate.
 4. The method of claim 1, comprising forming a memory device.5. The method of claim 1, wherein the PCMO structure comprises a layerof with a thickness of 2,000 Å or less.
 6. The method of claim 1,comprising depositing materials using a radio frequency (RF) rate of13.56 Megahertz.
 7. The method of claim 1, comprising: providing atleast one target and a substrate having a film-forming surface portionand a back portion; creating a magnetic field so that the film-formingsurface portion is placed in the magnetic field with the magnetic fieldinduced normal to the substrate surface portion; back-biasing the backportion of the substrate; and sputtering material onto the film-formingsurface portion, wherein the thin forming surface portion comprisesnon-volatile data storage devices interconnected thereto.
 8. A facingtargets sputtering device for semiconductor fabrication, comprising: anair-tight chamber in which an inert gas is admittable and exhaustible; apair of target plates placed at opposite ends of said air-tight chamberrespectively so as to face each other and form a plasma regiontherebetween; a pair of magnets respectively disposed adjacent to saidtarget plates such that magnet poles of different polarities face eachother across said plasma region thereby to establish a magnetic field ofsaid plasma region between said target plates; a substrate holderdisposed adjacent to said plasma region, said substrate holder adaptedto hold a substrate on which an alloyed thin film is to be deposited; aback-bias power supply coupled to the substrate holder; wherein thesubstrate includes one or more memory arrays formed thereon, wherein theargon gas and oxygen gas flows into the deposition chamber at a lowoxygen flow rate approximately between 0 and ten percent (10%) of anargon flow rate, a pressure approximately between 2×10⁻⁵ Torr and 1×10⁻³Torr, and a deposition temperature approximately between 340° C. and450° C. on a sputtering target with PCMO (Pr_(1-x)Ca_(x)MnO₃, where X isbetween 0.1 and 0.9) and wherein a first reference cell containing afirst resistor of a first resistance value; a second reference cellcontaining a second resistor of a second resistance value, wherein acurrent source is coupled to said first and second reference cells forpassing a current through said first and second reference cells, andwherein said first and second reference cells are coupled to each otherso as to enable a detection of a reference voltage to be fed into aninput of a comparator for comparing said reference voltage with avoltage sensed from a selected memory cell of said memory array.
 9. Afacing targets sputtering device according to claim 11, wherein theback-bias power supply is a DC or an AC electric power source.
 10. Afacing targets sputtering device according to claim 11, furthercomprising a first target power supply coupled to one of the targetplates.
 11. A facing targets sputtering device according to claim 13,wherein the first target power supply is a DC or an AC electric powersource.
 12. A facing targets sputtering device according to claim 11,further comprising a second target power supply coupled to the remainingtarget plate.
 13. A facing targets sputtering device according to claim11, wherein the first and second target power supplies comprises DC andAC electric power sources.
 14. A facing targets sputtering deviceaccording to claim 11, further comprising a robot arm to move the wafer.15. A facing targets sputtering device according to claim 11, furthercomprising a magnetron coupled to the chamber.
 16. A facing targetssputtering device according to claim 11, further comprising a chuckheater mounted above the wafer.
 17. The apparatus of claim 11, whereinthe FTS further comprises first and second targets mounted in parallel.